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MC14069UB Hex Inverter
The MC14069UB hex inverter is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.
http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 P SUFFIX CASE 646 MC14069UBCP AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 500 - 55 to +125 - 65 to +150 260 mW C C C SOEIAJ-14 F SUFFIX CASE 965 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week 14 MC14069U AWLYWW 14 069U ALYW
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-Power TTL Loads or One Low-Power * * *
Schottky TTL Load Over the Rated Temperature Range Triple Diode Protection on All Inputs Pin-for-Pin Replacement for CD4069UB Meets JEDEC UB Specifications
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 Unit V V mA
14069U AWLYWW
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
Device MC14069UBCP MC14069UBD MC14069UBDR2 MC14069UBDT Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 Shipping 2000/Box 2750/Box 2500/Tape & Reel 96/Rail
v
v
MC14069UBDTEL TSSOP-14 2000/Tape & Reel MC14069UBDTR2 TSSOP-14 2500/Tape & Reel MC14069UBF MC14069UBFEL SOEIAJ-14 SOEIAJ-14 See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14069UB/D
MC14069UB
PIN ASSIGNMENT
IN 1 OUT 1 IN 2 OUT 2 IN 3 OUT 3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 6 OUT 6 IN 5 OUT 5 IN 4 OUT 4
LOGIC DIAGRAM
1 3 5 9 11 13 2 4 6 8 10 12 VDD = PIN 14 VSS = PIN 7
CIRCUIT SCHEMATIC (1/6 OF CIRCUIT SHOWN)
VDD
INPUT*
OUTPUT
VSS *Double diode protection on all inputs not shown.
20 ns VDD 14 PULSE GENERATOR INPUT 7 VSS CL OUTPUT INPUT tPHL OUTPUT 90% 50% 10% tTHL tTLH 90% 50% 10%
20 ns VDD VSS VOH VOL
tPLH
Figure 1. Switching Time Test Circuit and Waveforms
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4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Propagation Delay Times (5.) (CL = 50 pF) tPLH, tPHL = (0.90 ns/pF) CL + 20 ns tPLH, tPHL = (0.36 ns/pF) CL + 22 ns tPLH, tPHL = (0.26 ns/pF) CL + 17 ns
Output Rise and Fall Times (5.) (CL = 50 pF) tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.60 ns/pF) CL + 20 ns tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Gate) (CL = 50 pF)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc)
Output Voltage Vin = VDD
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc)
Vin = 0
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"0" Level
"1" Level
"0" Level
Source
Sink
Symbo l
tPLH, tPHL
tTLH, tTHL
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95
MC14069UB
4.0 8.0 12.5
0.64 1.6 4.2
MinIII Max
-- -- --
-- -- --
-- -- --
--
--
-- -- --
-- -- --
- 55_C
3 0.1 0.25 0.5 1.0 0.05 0.05 0.05 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 4.0 8.0 12.5 0.51 1.3 3.4 IT = (0.3 A/kHz) f + IDD/6 IT = (0.6 A/kHz) f + IDD/6 IT = (0.9 A/kHz) f + IDD/6 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (4.) 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 100 50 40 5.0 5.0 10 15 65 40 30 0 0 0 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 125 75 55 200 100 80 7.5 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 4.0 8.0 12.5 0.36 0.9 2.4 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF ns ns
MC14069UB
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14 8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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MC14069UB
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC14069UB
PACKAGE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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CCC EE CCC EE
SECTION N-N -W-
MC14069UB
PACKAGE DIMENSIONS
F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14069UB
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MC14069UB/D

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